`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   00:46:03 11/22/2014
// Design Name:   Fifo
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/Xilin/uart-arquitectura-2014/FifoTest.v
// Project Name:  UART
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Fifo
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module FifoTest;

	// Inputs
	reg clk;
	reg reset;
	reg rd;
	reg wr;
	reg [7:0] w_data;

	// Outputs
	wire full;
	wire empty;
	wire [7:0] r_data;

	// Instantiate the Unit Under Test (UUT)
	Fifo uut (
		.clk(clk), 
		.reset(reset), 
		.rd(rd), 
		.wr(wr), 
		.w_data(w_data), 
		.full(full), 
		.empty(empty), 
		.r_data(r_data)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 1;
		rd = 0;
		wr = 0;
		w_data = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 0;  
		// Add stimulus here
		w_data = 8'b 00001111;
		wr = 1;
		#20
		wr = 0;
		#100
		w_data = ~(8'b 00001111);
		wr = 1;
		#20
		wr = 0;
		#100
		w_data = ~(8'b 10101010);
		wr = 1;
		#20
		wr = 0;
		#100
		w_data = (8'b 10101010);
		wr = 1;
		#20
		wr = 0;
		#100
		rd = 1;
		#20
		rd = 0;
		#100
		//w_data = 8'b 11011011;
		//wr = 1;
		rd = 1;
		#20
		//wr = 0;
		rd = 0;
		#100
		rd = 1;
		#20
		rd = 0;
		#100
		rd = 1;
		#20
		rd = 0;
		
	end
	
 always begin
	#10
	clk = ~clk;
end
      
endmodule

